The present invention relates generally to an integrated circuit (IC) layout design, and more particularly to the implementation of interleaved dummy conductive segments to simplify a rerouting of electrical connections.
The designing and fabricating ICs have become more difficult, due to the increasingly smaller device size and more complicated circuit designs, as the semiconductor technology advances. The circuit complexity and device density often create design errors, such as electrical circuit errors, design rule violations, pattern congestion, timing errors, noise, crosstalk, etc. In order to correct these errors, a redesign of the IC is required by engineering change orders (ECOs). One typical ECO is to reroute the electrical connection from a first node to a second node of the IC. The electrical connection is often composed of a plurality of metal lines on various metal layers, and certain interconnection units interposed there among. A rerouting usually requires a change of at least three layers, two layers for the metal lines, and one layer for the interconnection units. From the fabrication point of view, each of the three layers requires a separate mask to define its patterns. This means that a change of design will necessitate a redesign of the three masks for the three layers. In some worse cases, a change of design often involves more than five masks. This incurs significant costs.
Therefore, desirable in the art of IC designs are new layouts and methods to simplify the process in rerouting of electrical connections.